Conventional method to manufacture a capacitor on a memory device (e.g. DRAM) is shown in FIG. 1. The processes are described from top to bottom in FIG. 1, wherein a source 2 (or drain) of a transistor is formed in a wafer substrate 1 first, and then a layer of dielectric 3 is deposited on top of the substrate 1, followed by etching through the dielectric 3 on top of the source 2 to form a node contact hole 4, polysilicon 41 is then filled into the node contact hole 4, followed by steps to form a electrode 5 of the capacitor, the dielectric 6, and the other electrode 7 of the capacitor. However, the above method makes the capacitor occupy too much area, and can not increase the capacitance.
In order to reduce the area occupied by the capacitor and increase the capacitance, a capacitor with crown-shape is adopted. As shown in FIG. 2, the electrode 5 of the capacitor is formed into a cylinder with crown-shape, the dielectric 6 and the other electrode 7 are then deposited on top of the electrode 5 sequentially so as to increase the electrode area of the capacitor, raise the capacitance, and reduce the area occupied by the capacitor.
However, the capacitor formed by the method shown in FIG. 2 is generally symmetrical to the node contact hole 4, which makes the manufacturing process very complicated and the cost is therefore increased.